The present invention relates to manufacturing methods of semiconductor devices, and more particularly, to a technique effectively applied to a manufacturing method of a semiconductor device with a metal insulator semiconductor field effect transistor (MISFET).
The MISFET(MIS field effect transistor, MIS transistor) can be formed by forming a gate insulating film over a semiconductor substrate, forming a gate electrode over the gate insulating film, and then forming source and drain regions by ion implantation or the like.
Japanese Unexamined Patent Publication No. 2001-156059 (Patent Document 1) discloses a technique which involves forming low-concentration source and drain regions by ion implantation after formation of an insulating coating, removing the insulating coating, forming sidewalls of oxide films, and then forming high-concentration source and drain regions 21 by ion implantation.
Japanese Unexamined Patent Publication No. 2003-100902 (Patent Document 2) discloses a technique which involves performing extension ion implantation using offset sidewalls.
Japanese Unexamined Patent Publication No. 2008-117848 (Patent Document 3) discloses a technique which involves forming an extension region using an offset spacer.
Japanese Unexamined Patent Publication No. 2008-171910 (Patent Document 4) discloses a technique which involves forming a source and drain extension region using an offset spacer.